The digital interface between radio frequency integrated circuits (RFICs) and baseband integrated circuits (BBIC) has to support increasingly high data rates with wireless communication standards such as the Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard employing carrier aggregation. Digital interface standards are specified by the Mobile Industry Processor Interface (MIPI) Alliance. The current MIPI DigRF v4 draft interface requires a 5.2 GHz clock for transmitting data in the LTE 20+20+20 case, denoting aggregation of three 20 MHz portions of spectrum, rendering the physical implementation very challenging. These extremely high clock rates are required because the clock and data is transmitted with a single differential line. As an alternative, a three-wire interface is under consideration by the MIPI Alliance. This alternative interface uses three-level signals transmitted over three wires resulting in six unique states for data coding, so that theoretically log2(6) bits≈2.585 bits can be transmitted with three wires in one data transmission cycle. If the data is forced to change state every data transmission cycle, five unique states can be used to transfer theoretically log2(5) bits≈2.322 bits of data, while also a clock signal can be extracted from the changes in the transmitted signals. Furthermore, by permitting the data to change at both the rising and falling edges of a clock signal, a technique known as Double Data Rate (DDR), the data rate can be further doubled. However, the high bit rates required for the LTE carrier aggregation modes push the operating frequencies of the phase locked loop employed for clock synchronisation into the same range as employed by a frequency synthesizer incorporated in the RFIC. This means that the power consumption of the phase locked loop becomes comparable to the power consumption of the RFIC frequency synthesizer. Moreover, special radio frequency (RF) device modelling, and even special RF devices, such as varactors, are required to implement DigRF v4. In addition, known three-wire digital interfaces require a non-zero voltage difference between each pair of the wires.